HI-3584A

The HI-3584A is a silicon gate CMOS device for interfacing a 3.3V 16-bit parallel data bus to the ARINC 429 serial bus. The HI-3584A design offers a high-speed host CPU interface compared with the earlier HI-3584 product. The device provides two receivers each with label recognition, a 32 by 32 FIFO, and an analog line receiver. Up to 16 labels may be programmed for each receiver. The independent transmitter also has a 32 by 32 FIFO. The status of all three FIFOs can be monitored using the external status pins, or by polling the HI-3584’s status register.

Other new features include a programmable option of data or parity in the 32nd bit and the ability to unscramble the 32-bit word. Also, versions are available with different values of input resistance to allow users to more easily add external lightning protection circuitry.

The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The databus and all control signals are CMOS and TTL compatible.

The 3.3V HI-3584A applies the ARINC protocol to the receivers and transmitter. Timing is based on a 1 Megahertz clock.

Additional interface circuitry such as the Holt HI-8585, HI-8586, HI-8570 or HI-8571 is required to translate the transmitter’s 3.3V volt logic outputs to ARINC 429 drive levels.