HI-6120
3.3V operation. Integrated dual transceivers. 32K x 16 RAM, illegal command detection, data buffering, time tag, optional auto initialization, 16-bit parallel host interface.
The HI-6120 and HI-6121 provide a complete, integrated, 3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a 100-pin plastic quad flat pack (PQFP). The HI-6121 has a 4-wire SPI (Serial Peripheral Interface) host connection and comes in a reduced pin count 52-pin PQFP or 64-pin QFN.
Both devices handle all aspects of the MIL-STD- 1553 protocol, including message encoding, decoding, error detection, illegal command detection and data buffering. Host data management is simplified by storing message information and data within the on-chip 32K x 16 static RAM.
Key Features
- MIL-STD-1553B/C, MIL-STD-1760, SAE AS15531A and STANAG 3838 compliant
- Third Party RT Validated
- Four data buffer methods for subaddress transmit and receive commands: indexed (single) buffering, pingpong (double) buffering and two circular buffer modes
- Independently selectable data buffer modes for transmit and receive commands on each subaddress
- Simplified mode code command handling
- Integral 16-bit Time-Tag counter has programmable options for clock, interrupts and auto-synchronization
- Message information and time-tag words are stored with message data words for all transacted messages
- In compliance with MIL-STD-1553B Notice 2, received data from broadcast messages may be optionally separated from non-broadcast received data
- Optional interrupt log buffer stores the most recent 16 interrupts to minimize host service duties
- Optional illegal command detection uses internal table
- Optional automatic self-initialization at reset
- MIL-STD-1760 compliant
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Technical Specifications
| Release Date | 2009 |
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| Applications |
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Downloads
| Datasheet | Click to view Datasheet (PDF) |
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